智能温度报警器 温度报警器外文翻译

毕业设计（论文）外文翻译 题 目: 基于51单片机温度报警器的设计 英文题目: 51 MCU-based design of a temperature alarm 系 别: ______ 信息工程系_ 专 业: ______ 电子信息工程_______ 班 级: ______ ___________ 学 号: _______ ________ 姓 名: __ ________ _____________ 指导老师: ________ ____________ 填表日期: ________ ________ 单片机 　 单片机是指一个集成在一块芯片上的完整计算机系统。尽管他的大部分功能集成在一块小芯片上，但是它具有一个完整计算机所需要的大部分部件：CPU、内存、内部和外部总线系统，目前大部分还会具有外存。同时集成诸如通讯接口、定时器，实时时钟等外围设备。而现在最强大的单片机系统甚至可以将声音、图像、网络、复杂的输入输出系统集成在一块芯片上。

单片机也被称为微控制器（Microcontroller），是因为它最早被用在工业控制领域。单片机由芯片内仅有CPU的专用处理器发展而来。最早的设计理念是通过将大量外围设备和CPU集成在一个芯片中，使计算机系统更小，更容易集成进复杂的而对提及要求严格的控制设备当中。INTEL的Z80是最早按照这种思想设计出的处理器，从此以后，单片机和专用处理器的发展便分道扬镳。

早期的单片机都是8位或4位的。其中最成功的是INTEL的8031，因为简单可靠而性能不错获得了很大的好评。此后在8031上发展出了MCS51系列单片机系统。基于这一系统的单片机系统直到现在还在广泛使用。随着工业控制领域要求的提高，开始出现了16位单片机，但因为性价比不理想并未得到很广泛的应用。90年代后随着消费电子产品大发展，单片机技术得到了巨大的提高。随着INTEL i960系列特别是后来的ARM系列的广泛应用，32位单片机迅速取代16位单片机的高端地位，并且进入主流市场。而传统的8位单片机的性能也得到了飞速提高，处理能力比起80年代提高了数百倍。目前，高端的32位单片机主频已经超过300MHz，性能直追90年代中期的专用处理器，而普通的型号出厂价格跌落至1美元，最高端的型号也只有10美元。当代单片机系统已经不再只在裸机环境下开发和使用，大量专用的嵌入式操作系统被广泛应用在全系列的单片机上。而在作为掌上电脑和手机核心处理的高端单片机甚至可以直接使用专用的Windows和Linux操作系统。

8051单片机由运算器、控制器、寄存器等组成。运算器以完成二进制的算术/逻辑运算部件ALU为核心，再加上暂存器TMP、累加器ACC、寄存器B、程序状态标志寄存器PSW及布尔处理器。累加器ACC是一个八位寄存器，它是CPU中工作最频繁的寄存器。在进行算术、逻辑运算时，累加器ACC往往在运算前暂存一个操作数（如被加数），而运算后又保存其结果（如代数和）。寄存器B主要用于乘法和除法操作。标志寄存器PSW也是一个八位寄存器，用来存放运算结果的一些特征，如有无进位、借位等。其每位的具体含意如下所示。PSW CY AC FO RS1 RS0 OV—P对用户来讲，最关心的是以下四点。

1. 进位标志CY（PSW7）。它表示了运算是否有进位（或借位）。如果操作结果在最高位有进位（加法）或者借位（减法），则该位为1，否则为0。2. 2. 辅助进位标志AC。又称半进位标志，它反映了两个八位数运算低四位是否有半进位，即低四位相加（或减）有否进位（或借位），如有则AC为1状态，否则为0。

3. 溢出标志位OV。MCS—1反映带符号数的运算结果是否有溢出，有溢出时，此位为1，否则为0。

4. 奇偶标志P。反映累加器ACC内容的奇偶性，如果ACC中的运算结果有偶数个1（如11001100B，其中有4个1），则P为0，否则，P=1。PSW的其它位，将在以后再介绍。由于PSW存放程序执行中的状态，故又叫程序状态字，运算器中还有一个按位（bit）进行逻辑运算的逻辑处理机（又称布尔处理机）。其功能在介绍位指令时再说明。关于控制器，控制器是CPU的神经中枢，它包括定时控制逻辑电路、指令寄存器、译码器、地址指针DPTR及程序计数器PC、堆栈指针SP等。这里程序计数器PC是由16位寄存器构成的计数器。要单片机执行一个程序，就必须把该程序按顺序预先装入存储器ROM的某个区域。单片机动作时应按顺序一条条取出指令来加以执行。因此，必须有一个电路能找出指令所在的单元地址，该电路就是程序计数器PC。当单片机开始执行程序时，给PC装入第一条指令所在地址，它每取出一条指令（如为多字节指令，则每取出一个指令字节），PC的内容就自动加1，以指向下一条指令的地址，使指令能顺序执行。只有当程序遇到转移指令、子程序调用指令，或遇到中断时，PC才转到所需要的地方去。8051 CPU指定的地址，从ROM相应单元中取出指令字节放在指令寄存器中寄存，然后，指令寄存器中的指令代码被译码器译成各种形式的控制信号，这些信号与单片机时钟振荡器产生的时钟脉冲在定时与控制电路中相结合，形成按一定时间节拍变化的电平和时钟，即所谓控制信息，在CPU内部协调寄存器之间的数据传输、运算等操作。

再来介绍一下存储器，存储器是单片机的又一个重要组成部分，有一种存储容量为256个单元的存储器结构。其中每个存储单元对应一个地址，256个单元共有256个地址，用两位16进制数表示，即存储器的地址（00H～FFH）。存储器中每个存储单元可存放一个八位二进制信息，通常用两位16进制数来表示，这就是存储器的内容。存储器的存储单元地址和存储单元的内容是不同的两个概念，不能混淆。单片机还包括程序存储器。程序是控制计算机动作的一系列命令，单片机只认识由“0”和“1”代码构成的机器指令。如前述用助记符编写的命令MOV A，#20H，换成机器认识的代码74H、20H：（写成二进制就是01110100B和00100000B）。在单片机处理问题之前必须事先将编好的程序、表格、常数汇编成机器代码后存入单片机的存储器中，该存储器称为程序存储器。程序存储器可以放在片内或片外，亦可片内片外同时设置。由于PC程序计数器为16位，使得程序存储器可用16位二进制地址，因此，内外存储器的地址最大可从0000H到FFFFH。8051内部有4k字节的ROM，就占用了由0000H～0FFFH的最低4k个字节，这时片外扩充的程序存储器地址编号应由1000H开始，如果将8051当做8031使用，不想利用片内4kROM，全用片外存储器，则地址编号仍可由0000H开始。不过，这时应使用EA脚，保持低电平。当EA为高电平时，用户在0000H至0FFFH范围内使用内部ROM，大于0FFFH后，单片机CPU自动访问外部程序存储器。单片机的数据存储器由读写存储器RAM组成。其最大容量可扩展到64k，用于存储实时输入的数据。8051内部有256个单元的内部数据存储器，其中00H～7FH为内部随机存储器RAM，80H～FFH为专用寄存器区。实际使用时应首先充分利用内部存储器，从使用角度讲，搞清内部数据存储器的结构和地址分配是十分重要的。因为将来在学习指令系统和程序设计时会经常用到它们。8051内部数据存储器地址由00H至FFH共有256个字节的地址空间，该空间被分为两部分，其中内部数据RAM的地址为00H～7FH（即0～127）。而用做特殊功能寄存器的地址为80H～FFH。在此256个字节中，还开辟有一个所谓“位地址”区，该区域内不但可按字节寻址，还可按“位（bit）”寻址。对于那些需要进行位操作的数据，可以存放到这个区域。从00H到1FH安排了四组工作寄存器，每组占用8个RAM字节，记为R0～R7。究竟选用那一组寄存器，由前述标志寄存器中的RS1和RS0来选用。在这两位上放入不同的二进制数，即可选用不同的寄存器组。

特殊功能寄存器（SFR）的地址范围为80H～FFH。在MCS－51中，除程序计数器PC和四个工作寄存器区外，其余21个特殊功能寄存器都在这SFR块中。其中5个是双字节寄存器，它们共占用了26个字节。各特殊功能寄存器的符号和地址。其中带*号的可位寻址。特殊功能寄存器反映了8051的状态，实际上是8051的状态字及控制字寄存器。用于CPU PSW便是典型一例。这些特殊功能寄存器大体上分为两类，一类与芯片的引脚有关，另一类作片内功能的控制用。与芯片引脚有关的特殊功能寄存器是P0～P3，它们实际上是4个8位锁存器（每个I/O口一个），每个锁存器附加有相应的输出驱动器和输入缓冲器就构成了一个并行口。MCS－51共有P0～P3四个这样的并行口，可提供32根I/O线，每根线都是双向的，并且大都有第二功能。其余用于芯片控制的寄存器中，累加器A、标志寄存器PSW、数据指针DPTR等的功能前已提及。

下面再来谈论如何让单片机如何正常工作。单片机要正常运作，事先需编制程序，再把程序放入存贮器中，然后由CPU执行该程序。程序是由指令组成的，指令的基本组成是操作码和操作数。单片机的品种很多，设计时怎样表示操作码和操作数，都有各自的规定，再有指令代码也各不相同，因此，必须对所选单片机的全部指令，也就是所谓“指令系统”，有足够的了解。各个系列的单片机虽然有不同的指令系统，但也有其共同性。掌握一种单片机的指令系统，对其它系列单片机可以起到触类旁通的作用。MCS－51单片机应用广泛、派生品种多、具有代表性 。所以，这里以MCS－51系列的指令系统为例说明“指令”的组成和应用。例子1，MOV A，#20H：这条指令表示把20H这个数送入累加器A中（一个特殊功能寄存器）。例子2，ADD A，70H：这条指令表示把累加器A中的内容（在上例中送入的#20H）和存贮器中地址为70H单元中的内容（也是一个数字），通过算术逻辑单元（英文缩写为ALU）相加，并将结果保留在A中。这里MOV、ADD等称为操作码，而A、#20H、70H等均称为操作数。在汇编语言程序中，操作码通常由英文单词缩写而成，这样有助于记忆，所以又称助记符。如MOV就是英文单词MOVE的缩写，含有搬移的意思；
而ADD即为英文单词，其意为相加。因此，对于略懂英语的用户，掌握单片机指令的含意是较为方便的。操作数有多种表示法，如以上的#20H称为立即数，即20H就是真正的操作数。而70H是存贮器中某个单元的地址，在该单元中，放着操作数（比如说是3AH），ADDA，70H不是将70H和A中的内容相加，而是从存贮器70H单元中将3AH取出和A中的内容相加。由上可知，要找到实际操作数，有时就要转个弯，甚至转几个弯，这个过程称为寻址4：操作数放在RAM某个单元中，该单元的地址又放在寄存器R0或R1中。

如果RAM的地址大于256，则该地址存放在16位寄存器DPTR（数据指针）中，此时在寄存器名前加@符号来表示这种间接寻址。如MOV A，@ R0。其它还有变址寻址、相对寻址、位寻址等，待以后再详细介绍。可能有人会问，在指令中直接给出实际操作数，不是简单明了吗？为什么还要用其它几种寻址方式呢？这是因为在编制程序时很难一下子就给出操作数。如用单片机控制温度时，时时需要将给定的控制温度（如20℃）减去环境温度，而环境温度时时有变化，显然无法在程序指令中给出，只有通过一定方式，将其送入某个输入/输出口，再存放在某个寄存器中，这就必须用到寄存器寻址。又如要进行算术运算，要计算每班学员各科成绩的平均值，如果把每个学员的各科都编一个程序，在程序中直接给出该学员各科成绩，再求平均值，显然太麻烦。这里可以编一个求平均成绩的通用程序，把每位学员的成绩送入存贮器的各个单元中，这时可采取直接寻址，一个程序可供每个学员用，不是更方便吗？所以，寻址方式越多，编制程序就越方便、灵活，适用范围就越广，寻址有如找人，如被找的人有手机、BP机、座机电话等多种联系方式则就容易找到他，单片机也是如此，寻址方式越多，找操作数越方便，单片机的功能就越强。前面介绍51系列单片机的寻址方式时，常遇到单片机内部的一些寄存器、累加器A、通用寄存器R0～R7、数据指针DPTR和存贮器等。在以后介绍指令时，数据就要在这些寄存器、存贮器之间传送，或者进行运算。因此，编制程序就需熟悉单片机的内部结构。8051单片机的内部总体结构其基本特性：8位CPU、片内振荡器、4k字节ROM、128字节RAM、21个特殊功能寄存器、32根I/O线可寻址的64k字节外部数据、程序存贮空间、2个16位定时器、计数器,中断结构：具有二个优先级、五个中断源、一个全双口串行口位寻址（即可寻找某位的内容）功能，适于按位进行逻辑运算的位处理器。除128字节RAM、4k字节ROM和中断、串行口及定时器模块外，还有4组I/O口P0～P3，余下的就是CPU的全部组成。把4kROM换为EPROM就是8751的结构，如去掉ROM/EPROM部分即为8031的框图，如果将ROM置换为Flash存贮器或EEPROM，或再省去某些I/O，即可得到51系列的派生品种，如89C51、AT89C2051等单片机的框图。单片机各部分是通过内部的总线有机地连接起来的。

下面再谈AT89C51单片机性能介绍。AT89C51是一种带4K字节闪烁可编程可擦除只读存储器（FPEROM—Flash :Programmable and Erasable Read Only Memory）的低电压，高性能CMOS8位微处理器，俗称单片机。该器件采用ATMEL高密度非易失存储器制造技术制造，与工业标准的MCS-51指令集和输出管脚相兼容。由于将多功能8位CPU和闪烁存储器组合在单个芯片中，ATMEL的AT89C51是一种高效微控制器，为很多嵌入式控制系统提供了一种灵活性高且价廉的方案。

1.主要特性:与MCS-51兼容,4K字节可编程闪烁存储器,寿命：1000写/擦循环，数据保留时间：10年，全静态工作：0Hz-24Hz，三级程序存储器锁定，128*8位内部RAM，32可编程I/O线，两个16位定时器/计数器，5个中断源，可编程串行通道，低功耗的闲置和掉电模式，片内振荡器和时钟电路。

2.管脚说明：VCC：供电电压，GND：接地，P0口：P0口为一个8位漏级开路双向I/O口，每脚可吸收8TTL门电流。当P1口的管脚第一次写1时，被定义为高阻输入。P0能够用于外部程序数据存储器，它可以被定义为数据/地址的第八位。在FIASH编程时，P0 口作为原码输入口，当FIASH进行校验时，P0输出原码，此时P0外部必须被拉高。

P1口：P1口是一个内部提供上拉电阻的8位双向I/O口，P1口缓冲器能接收输出4TTL门电流。P1口管脚写入1后，被内部上拉为高，可用作输入，P1口被外部下拉为低电平时，将输出电流，这是由于内部上拉的缘故。在FLASH编程和校验时，P1口作为第8位地址接收。

P2口：P2口为一个内部上拉电阻的8位双向I/O口，P2口缓冲器可接收，输出4个TTL门电流，当P2口被写“1”时，其管脚被内部上拉电阻拉高，且作为输入。并因此作为输入时，P2口的管脚被外部拉低，将输出电流。这是由于内部上拉的缘故。P2口当用于外部程序存储器或16位地址外部数据存储器进行存取时，P2口输出地址的高八位。在给出地址“1”时，它利用内部上拉优势，当对外部8位地址数据存储器进行读写时，P2口输出其特殊功能寄存器的内容。P2口在FLASH编程和校验时接收高8位地址信号和控制信号。

P3口：P3口管脚是8个带内部上拉电阻的双向I/O口，可接收输出4个TTL门电流。当P3口写入“1”后，它们被内部上拉为高电平，并用作输入。作为输入，由于外部下拉为低电平，P3口将输出电流（ILL）这是由于上拉的缘故。P3口也可作为AT89C51的一些特殊功能口：P3.0 RXD（串行输入口）、P3.1 TXD（串行输出口）、P3.2 /INT0（外部中断0）、P3.3 /INT1（外部中断1）、P3.4 T0（记时器0外部输入）、P3.5 T1（记时器1外部输入）、P3.6 /WR（外部数据存储器写选通）、P3.7 /RXD（外部数据存储器读选通）。P3口同时为闪烁编程和编程校验接收一些控制信号。

RST：复位输入。当振荡器复位器件时，要保持RST脚两个机器周期的高电平时间。

ALE/PROG：当访问外部存储器时，地址锁存允许的输出电平用于锁存地址的地位字节。在FLASH编程期间，此引脚用于输入编程脉冲。在平时，ALE端以不变的频率周期输出正脉冲信号，此频率为振荡器频率的1/6。因此它可用作对外部输出的脉冲或用于定时目的。然而要注意的是：每当用作外部数据存储器时，将跳过一个ALE脉冲。如想禁止ALE的输出可在SFR8EH地址上置0。此时， ALE只有在执行MOVX，MOVC指令是ALE才起作用。另外，该引脚被略微拉高。如果微处理器在外部执行状态ALE禁止，置位无效。

/PSEN：外部程序存储器的选通信号。在由外部程序存储器取指期间，每个机器周期两次/PSEN有效。但在访问外部数据存储器时，这两次有效的/PSEN信号将不出现。/EA/VPP：当/EA保持低电平时，则在此期间外部程序存储器（0000H～FFFFH），不管是否有内部程序存储器。注意加密方式，/EA将内部锁定为RESET；
当/EA端保持高电平时，此间内部程序存储器。在FLASH编程期间，此引脚也用于施加12V编程电源（VPP）。

XTAL1：反向振荡放大器的输入及内部时钟工作电路的输入。

XTAL2：来自反向振荡器的输出。

振荡器：XTAL1和XTAL2分别为反向放大器的输入和输出。该反向放大器可以配置为片内振荡器。石晶振荡和陶瓷振荡均可采用。如采用外部时钟源驱动器件，XTAL2应不接。有余输入至内部时钟信号要通过一个二分频触发器，因此对外部时钟信号的脉宽无任何要求，但必须保证脉冲的高低电平要求的宽度。

芯片擦除：
整个PEROM阵列和三个锁定位的电擦除可通过正确的控制信号组合，并保持ALE管脚处于低电平10ms 来完成。在芯片擦操作中，代码阵列全被写“1”且在任何非空存储字节被重复编程以前，该操作必须被执行。此外，AT89C51设有稳态逻辑，可以在低到零频率的条件下静态逻辑，支持两种软件可选的掉电模式。在闲置模式下，CPU停止工作。

但RAM，定时器，计数器，串口和中断系统仍在工作。在掉电模式下，保存RAM的内容并且冻结振荡器，禁止所用其他芯片功能，直到下一个硬件复位为止。

About Single-chip Refers to an integrated single-chip at a chip on the integrity of computer systems. Even though most of his features at a small chip on, but it has a complete computer most of the necessary components: CPU, memory, internal and external bus system, most will have the Core. At the same time, such as integrated communication interfaces, timers, real-time clock and other peripheral equipment. And now the most powerful single-chip microcomputer system can even voice, image, network, complex input and output of system integration on a single chip. Also known as single-chip microcontroller, because it is the first to be used in the field of industrial control. Single-chip by chip dedicated processor CPU only evolved. The first design concept through to a large number of peripherals and CPU in a single chip, the computer system so that smaller, more easily integrated into the complex and demanding with regard to the reference control devices. INTEL the Z80 is one of the earliest in accordance with this idea to design the processor, From then on, the MCU and the development of a dedicated processor parted ways. Early single-chip 8-bit or all of four. One of the most successful are Intel"s 8031, because the performance of a good reliable and easy access to great acclaim. Later on in 8031 developed a series of single-chip microcomputer system MCS51. Based on single-chip microcomputer system of the system is still widely used until now. As the field of industrial control requirements improve, beginning a 16-bit single-chip, but not ideal because cost-effective has not been very widely used. After the 90"s with the big consumer electronics product development, single-chip technology has been enormous improve. With INTEL i960 series, especially the later series of widely used ARM, 32-bit single-chip 16-bit single-chip microcomputer rapidly replacing high-end status, and enter the mainstream market. Whereas the traditional 8-bit MCU performance has been the rapid increase in processing power compared to the 80"s to raise a few hundred times. At present, the high-end single-chip 32 GHz has been more than 300MHz, the performance of close on the heels of the mid-90"s dedicated processor, while the general model ex-factory price dropped to one U.S. dollars, the most high-end models, only 10 U.S. dollars. Contemporary single-chip microcomputer system is no longer only in the bare-metal environment development and use of a large number of dedicated embedded operating system is widely used in on a full range of single-chip microcomputer. In the cell phone as a handheld computer and deal with high-end single-chip core can even direct the use of a dedicated Windows and Linux operating systems. Single-chip 8051 CPU by the operator and controller. Calculator to complete the binary arithmetic/logic operations Parts ALU at the core, together with registers on TMP, accumulator ACC, register B, the procedure register PSW status symbol and Boolean processor. Accumulator ACC is an eight registers, which are the most frequent job of CPU registers. In arithmetic, logic operations, the accumulator ACC is often a temporary one at pre-computing operands (such as being summand), and computing and then save the results (such as algebra and). Register B mainly used for multiplication and division operations. PSW register is also a mark of eight registers, used to store the results of some of the characteristics of computing, if not binary, and so on, and borrow. Its specific meaning of each are shown below. PSW CY AC FO RS1 RS0 OV-P to users, the most concerned about are the following four. First of all, the binary symbol CY (PSW7). Whether or not it has express a binary operator (or borrow bits). If the operation results at the highest level there is binary (addition) or borrow (subtraction), the bit is 1, otherwise to 0. Secondly, auxiliary binary symbol AC. Also known as semi-binary logo, it reflects both the number eight computing whether there is a half low of four binary, that is, the sum of the four low (or minus) has not binary (or borrow), and if there is AC for one status, otherwise to 0. Third, the overflow flag OV. MCS-1 to reflect the number of operator symbols with the results of whether there is any spill, there is spill, this bit is 1, otherwise to 0. Fourth, the parity symbol P. Reflect the content of accumulator ACC parity, if the ACC in an operation that results in even-numbered months have one (such as 11001100B, one of four there is one), then P is 0, otherwise, P = 1. PSW other places, will introduce at a later time. PSW stored procedures because of the status, it is also called the program status character have a calculator in bitwise (bit) to carry out logic operations logic processor (also known as Boolean processor). Its function in the introduction explain-bit instruction. About the controller, CPU controller is the nerve center, which includes the timing control logic circuit, an instruction register, decoder, address pointer DPTR and the program counter PC, stack pointer SP and so on. This program counter PC is 16-bit register consisting of counters. To single-chip implementation of a program, it is necessary to put the program into memory in advance in order ROM of an area. Single chip action should be taken out of a sequence of commands to be implemented. Therefore, we must have a circuit to find out where the command module address, the circuit is the program counter PC. When beginning the implementation of single-chip program, to the PC load instructions where the first address, it took out one of each command (such as for multi-byte instructions, each took out a command byte), PC will automatically add the contents of one to point to the next instruction address, so that instruction can be the order of implementation. Only when the process encountered in the transfer of instructions, subroutine call instructions, or encountered failure (after the introduction), PC only needed to go to go places. 8051 CPU"s designated address, the corresponding unit from the ROM command byte out on the instruction register in the storage, then, an instruction register of the instruction decoder code was translated into various forms of control signals, these single-chip signal and clock oscillator generated clock pulse in timing and control circuit combination of a certain period of time according to changes in electric calm beat the clock, the so-called control of information in the CPU internal coordination between the register data transfer, computing and other operations. Then tell us about memory, memory MCU are also an important component of has a storage capacity of 256 units of memory structure. One of each memory cell corresponds to an address, a total of 256 unit 256 addresses, use two 16 hexadecimal numbers, that is, memory address (00H ~ FFH). Memory of each memory cell can store one of eight binary information, usually using two 16-band number to express, and this is the contents of memory. Memory storage unit address and the contents of memory cells are two different concepts, should not confuse. Single-chip also includes the program memory. Process control computers are a series of action commands, Microcontroller Know only by "0" and "1" consisting of machine code instructions. Such as the preparation of the foregoing order with Mnemonic MOV A, # 20H, Know the code into the machine 74H, 20H: (written in binary is 01110100B and 00100000B). Problem in SCM is required before the deal will be good procedures, tables, constants compiled into machine code into single-chip memory, the memory referred to as program memory. Program memory can be put on the chip or chip, chip-chip can also be set up simultaneously. As the PC program counter to 16, making the procedure available for 16-bit binary memory addresses, therefore, both inside and outside the memory address from 0000H to the largest FFFFH. 8051 has 4k bytes of internal ROM, on the occupied by the 0000H ~ 0FFFH minimum 4k bytes, when the expansion of chip program memory address number shall be 1000h start, if you use 8051 as a 8031, do not want to use chip 4kROM , all used memory chip, then the address code can still start from 0000H.However, when EA feet should be used to maintain the low level. When EA is high, the user 0FFFH at 0000H to use internal ROM, more than 0FFFH, the single-chip CPU automatic access to external program memory. Single-chip data memory RAM memory by reading and writing components. Its maximum capacity can be expanded to 64k, used to store real-time input data. 8051 has 256 units within the internal data memory, one of 00H ~ 7FH for internal random access memory RAM, 80H ~ FFH area dedicated registers. Actual use should be the first full use of internal memory, from the use of perspective, to understand the structure of internal data memory and address of the distribution is very important. Since studying at the future directions of design systems and procedures will be frequently used them. 8051 internal data memory address 00H to FFH by a total of 256 bytes of address space, the space was divided into two parts, one of the internal data RAM address 00H ~ 7FH (that is, 0 ~ 127). The Special Function Registers to do with the address 80H ~ FFH. In this 256-byte also has opened up a so-called "digital address" area, the region can not only byte addressable, but also by the "bit (bit)" addressable. For those required to carry out the operation of the data bit can be stored into the region. From 00H to 1Fh arranged group of four working registers, each occupied by 8-byte RAM, recorded as R0 ~ R7. Whether the choice of which set of registers, from the aforementioned signs register in the selection of RS1 and RS0. Add on at these two different binary number, you can choose different registers. Special Function Register (SFR) address the range of 80H ~ FFH. At MCS-51, in addition to program counter register PC and four job outside the region, and the remaining 21 special function registers in this block in SFR. Are one of five double-byte register, and they take up a total of 26 bytes. Special Function Registers of the symbols and addresses, see Schedule 2. With * one of the available-bit addressing. Special Function Registers status reflects the 8051, 8051 are in fact the status word and control word register. CPU PSW is typical for a case. These Special Function Registers generally classified into two categories, one category with the pin on the chip, and the other for chip control function. Pin and chip-related special function registers are P0 ~ P3, they are in fact four of eight latches (one for each I / O port A), each has additional latch corresponding output driver and input buffers constitutes a parallel port. MCS-51 a total of P0 ~ P3 four such parallel port provides 32 I / O lines, each line are two-way, and large have the second function. The rest used for chip control registers, the accumulator A, signs register PSW, data pointers DPTR function mentioned before. Here again how to talk about how to make single-chip work correctly. Single-chip to normal operation to be programmed in advance, and then the procedure Add memory, and then by the CPU to implement the program. Procedures are composed by the instructions, directives are the basic components and operation of several op -code. A lot of single-chip varieties, how to express the design of op-code and operand, have their own requirements, and then there is instruction code varies, therefore, must be single-chip all the selected command, which is the so-called "instruction "there is enough understanding. Although the various series of single-chip systems have different commands, but also has its commonality. Master a single-chip instruction systems, to other series Single chip comprehend by analogy can play a role. MCS-51 single-chip applications, derived many varieties, representative, therefore, here to MCS-51 series of instruction as an example "command" the composition and application. Examples 1, MOV A, # 20H: The instructions said put the number of 20H into the accumulator A in (a special function register). Example 2, ADD A, 70H: This command put express accumulator A content (in the above example into the # 20H) and memory in the address of the content unit 70H (a figure), through the arithmetic logical unit (English abbreviation for the ALU) added together, the results remain in the A Medium. Here MOV, ADD, etc. known as the op-code, while the A, # 20H, 70H, all known as the operand. In assembly language programs, operation code is usually made by the English word acronym to help remember, therefore, also known as Mnemonic. English words such as MOV is the abbreviation of MOVE, which contains the meaning of the removal; and ADD is the English word, which means the sum. Therefore, users have some knowledge of English to grasp the meaning of single-chip instruction are more convenient. Operand has a wide range of express law, such as more than a few # 20H is called immediately, namely, 20H operand is true. And 70H is the memory address of a unit in the unit, placed operand (for example, are 3AH), ADD A, 70H instead of 70H and add the contents of A, but from memory 70H unit 3AH will remove the content and the sum of A. By up, we can see that the actual operation to find a few, and sometimes have to turn a corner, and even turn some bends, this process is known as addressable, MCS-51 a total of seven kinds of addressing, are presented below: First, immediately addressing: operand writing in the directive on, and on the procedures with op-code in memory. Put "#" is placed immediately in front of a few to express the way for addressing the immediate addressing, such as # 20H. Second, register addressing: operand on the register, in the directive to register the name directly to express operand address. For example, MOV A, R0 to belong to register addressing, the contents of register R0 is about to accumulator A Medium. Third, directly addressing: operand MCU internal RAM on a unit, in the instruction directly write the address of the module. Precedent such as the ADD A, 70H in 70H. Four, register indirect addressing: operand RAM on a particular unit, the unit"s address also on the register R0 or R1 Medium. If the address of RAM is greater than 256, the address stored in 16-bit register DPTR (data pointer), the time at the former register add @ symbol to indicate such an indirect addressing. Such as MOV A, @ R0. Other sides have variable addressing, relative addressing, bit-addressable and so on, to be detailed later. Some people might ask, in the instruction directly give the number of actual operation is not easy to understand? Why should we use several other addressable way This is because it is very difficult in the preparation of procedures immediately give operand. Such as using single-chip control of temperature, from time to time required to control a given temperature (such as 20 #) minus the ambient temperature, and ambient temperature has changed from time to time, apparently unable to give orders in the proceedings only through the way must be into an input / output port, and then stored in a register, which must be used for addressable register. Another example is to carry out arithmetic operations, various participants in each class to calculate the average score, if each student put the sections are made of a procedure, in the proceedings directly give the students grade subjects, and then for the average, it is clear too much trouble. Here can be made for an average grade of a common procedure, put each participant"s score into the various memory units, may be taken at this time directly addressing, a program for each student to use, not easier. Therefore, addressing the more programming more convenient and flexible, the scope of application of the more broad, addressing like to find people, such as people have been looking for cell phone, BP machine, landline phone, etc. Contacts are easy to find on He, single-chip microcomputer is also the case, addressing the more operands to find more convenient, single-chip functions of the stronger. In front of 51 family MCU introduce addressable manner, often encounter a number of internal single-chip registers, accumulator A, general-purpose registers R0 ~ R7, data pointer DPTR and the memory and so on. Introduction at a later instruction, the data is necessary in these registers, memory between the transmission, or conduct operations. Therefore, the establishment of procedures would need to be familiar with the internal structure of SCM. 8051 within the overall structure of its basic characteristics: 8-bit CPU, chip oscillator. 4k byte ROM, 128 bytes RAM, 21 special function registers, 32 I / O lines addressable 64k bytes external data, the program storage space, two 16-bit timers, counters, interrupt structure: with Priority 2, the five interrupt sources .A full dual-port serial port.-Bit addressing (you can search the contents of a) function, suitable for logic operations carried out by the bit processor. In addition to 128-byte RAM, 4k byte ROM and interruption, serial port and timer modules, there are 4 group I / O port P0 ~ P3, the remaining component is the CPU all. Put 4kROM for 8751 for the EPROM is the structure, such as removal of ROM / EPROM part of the diagram is 8031, if the ROM replacement for Flash memory or EEPROM, or re-save some I / O, you get 51 series derived species, such as 89C51, AT89C2051 MCU block diagram, etc.. Single chip are all parts of the bus through an internal organically linking. AT89C51 single-chip performance talk about the following introduction. AT89C51 is a flicker with 4K byte erasable programmable read-only memory (FPEROM-Falsh Programmable and Erasable Read Only Memory) of low-voltage, high-performance CMOS8 bit microprocessor, commonly known as single-chip microcomputer. The device ATMEL manufacture high-density nonvolatile memory technology with industry-standard MCS-51 Instruction set and output pin compatible. Because of the multi-purpose 8-bit CPU and flash memory chips in a single portfolio, ATMEL The AT89C51 is a high-performance microcontrollers, for a lot of embedded control system provides a flexible and inexpensive program. Main features: with the MCS-51 compatible, 4K bytes Programmable Flash Memory, Life expectancy: 1000 Writing / wipe cycle .. data retention time: 10 years. wholly static job: 0Hz-24Hz. Three-tier program memory lock. 128 * 8-bit internal RAM. 32 programmable I / O line. Two 16-bit timer / counter interrupt sources .5. Programmable serial channel. Low-power idle and power-down mode.?-chip oscillator and clock circuitry. Pin Description: VCC: power supply voltage. GND: Ground. P0 port: P0 mouth for a grade 8 open-drain bi-directional I / O port, each pin can absorb current 8TTL door. P1 pin when I first Writing 1, is defined as the high impedance input. P0 can be used for external program data memory, which can be defined as data / address bit eight. At FIASH programming, P0 port input as the original code, when FIASH to check when, P0 output of the original code, this time outside P0 must be pushed. P1 port: P1 port are provided on an internal pull-up resistor of 8 bi-directional I / O port, P1 mouth to receive the output buffer current 4TTL door. P1 pin I write one, she was an internal pull-high, can be used as input, P1 I was an external pull-down low when the output current, which is up because of internal reasons la. FLASH programming and calibration at the time, P1 mouth as eight-bit address to receive. P2 port: P2 mouth to an internal pull-up resistor on the 8-bit bi-directional I / O port, P2 I can receive buffers, the output current of 4 TTL door, when I was P2 Writing "1", the pin was on the internal push pull-up resistor, and as an input. And therefore as a type, P2 pin I was driving down the outside to output current. This is up because of internal reasons la. P2 mouth when used in external program memory or 16-bit address of the external data memory access time, P2 port output address high eight. Give the address at "1", it is the use of internal pull-advantage, when eight addresses on the external data memory read and write when, P2 I output the contents of special function registers. P2 mouth at FLASH programming and calibration receive high eight address signals and control signals. P3 mouth: P3 mouth are 8-pin with internal pull-up resistor on the bi-directional I / O port to receive the output current of 4 TTL door. P3 When I write "1", they were for internal pull-high, and used as input. As input, because of the external pull-down low, P3 will output current I (ILL) This is the reason because of pull up. P3 mouth can also be used as a number of special features AT89C51 mouth, as shown below: P3.0 RXD (serial input port). P3.1 TXD (serial output port). P3.2 / INT0 (external interrupt 0). P3.3 / INT1 (external interrupt 1). P3.4 T0 (timer 0 external input). P3.5 T1 (timer 1 external input). P3.6 / WR (external data memory write strobe). P3.7 / RD (external data memory read strobe) .P3 mouth at the same time flashing check programming and programming control signals to receive. RST: Reset input. When the oscillator device reset, the RST pin to maintain both the high machine cycle time. ALE / PROG: When access to external memory, the address latch to allow the output level for the latch status of the address byte. At FLASH programming period, this pin for input programming pulse. In peacetime, ALE client to change the frequency of cycle positive pulse output signal, the frequency of the oscillator frequency of 1 / 6. Therefore it can be used for external pulse output or for the purpose from time to time. However it should be noted that: Whenever used for external data memory, it will skip one ALE pulse. Want to prohibit such as ALE output can be at home on SFR8EH address 0. At this point, ALE is only in the implementation of MOVX, MOVC instructions are only the role of ALE. In addition, the pin has been slightly pushed up. If the microprocessor at the implementation status of external ALE prohibited, home digital invalid. / PSEN: external program memory of the Strobe. At by an external program memory access refers to the period, twice each machine cycle / PSEN effective. However, access to external data memory at the time, these two effective / PSEN signal will not occur. / EA / VPP: When / EA to maintain low-level, then during this period the external program memory (0000H-FFFFH), regardless of whether there is an internal program memory. Note: Encryption method, / EA will be locked for internal RESET; When / EA to maintain high-end, the internal program memory here. At FLASH programming period, this pin is also used to exert power 12V programming (VPP). XTAL1: reverse oscillation amplifier job input and internal clock circuit input. XTAL2: Output from the oscillator reverse. Oscillator: XTAL1 and XTAL2 are the reverse of the input and output amplifier. The amplifier can be configured to reverse-chip oscillator. Crystals and ceramic oscillation can be used. Such as the use of an external clock source drive device, XTAL2 should be no access. More than input to the internal clock signal through a two sub-frequency flip-flop, so the external clock signal pulse width without any request, but must ensure that the high-low pulse width requirements. Chip Erase: The entire array and three PEROM lock bit erase electricity through the correct combination of control signals and to maintain the ALE pin at the low 10ms to complete. At chip wipe operation, code arrays were all Writing "1" and in any non-empty memory byte has been programmed to repeat the past, the operation must be executed. In addition, AT89C51 has a steady-state logic, can be at low to zero frequency under the conditions of static logic, supports two software selectable power-down mode. At idle mode, CPU stop working. However, RAM, timers, counters, serial port and interrupt system are still working. At Power-down mode, to preserve the contents of RAM and freezing oscillator, the prohibition of the use of other chip functions until the next hardware reset date.

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